EDGA0=EDGA0_0, EDGA1=EDGA1_0, ONESHOTA=ONESHOTA_0, ARMA=ARMA_0, EDGCNTA_EN=EDGCNTA_EN_0, INP_SELA=INP_SELA_0
Capture Control A Register
| ARMA | Arm A 0 (ARMA_0): Input capture operation is disabled. 1 (ARMA_1): Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. |
| ONESHOTA | One Shot Mode A 0 (ONESHOTA_0): Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 1 (ONESHOTA_1): One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. |
| EDGA0 | Edge A 0 0 (EDGA0_0): Disabled 1 (EDGA0_1): Capture falling edges 2 (EDGA0_2): Capture rising edges 3 (EDGA0_3): Capture any edge |
| EDGA1 | Edge A 1 0 (EDGA1_0): Disabled 1 (EDGA1_1): Capture falling edges 2 (EDGA1_2): Capture rising edges 3 (EDGA1_3): Capture any edge |
| INP_SELA | Input Select A 0 (INP_SELA_0): Raw PWM_A input signal selected as source. 1 (INP_SELA_1): Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. |
| EDGCNTA_EN | Edge Counter A Enable 0 (EDGCNTA_EN_0): Edge counter disabled and held in reset 1 (EDGCNTA_EN_1): Edge counter enabled |
| CFAWM | Capture A FIFOs Water Mark |
| CA0CNT | Capture A0 FIFO Word Count |
| CA1CNT | Capture A1 FIFO Word Count |